TAREAS/TASKS:

- Development of compiler tools for RISC-V architectures with custom ISA extensions.

- Development of hardware accelerators for DSP and neuromorphic algoritms, integrated with RISC-V cores.

- Development of algorithm-to-hardware mapping mechanisms over regular computing structures (e.g., CGRAs).

HABILIDADES-CUALIFICACIONES/SKILLS-QUALIFICATIONS: 

Master degree on Electrical and Electronics Engineering, Computer Engineering or Computer Science. 

Previous experience with high-level programming languages and toolchains.

Previous experience with RISC-V architectures.

REQUERIMIENTOS ESPECIFICOS/SPECIFIC REQUIREMENTS:

- Embedded systems programming with C/C++.

- Basic competence on (parallel) computer architecture and digital system design with HDLs.

- Notion on RISC-V ISA and the intergration of custom accelerators.

BENEFICIOS/BENEFITS:

The contract includes a gross salary of 24000 € over 12 payments, and full social benefits in Spain. The salary level is competitive for the current situation in Madrid. Conference, summer school and workshop registration fees will be also covered.

CRITERIOS Y PROCESO DE SELECCION/ELIGIBILITY CRITERIA AND SELECTION PROCESS:

Se aplican las pautas establecidas en el proceso de selección del nuevo Reglamento para el proceso de selección y contratación del personal investigador, personal técnico y personal gestor relacionado con la investigación de la Universidad Politécnica de Madrid, aprobado en la UPM.

- Previous experience and knowledge on RISC-V and accelerator's extensions.

- Previous experience and knowledge on embedded systems programming with C/C++.

- Previous experience on IP design in VHDL and/or SystemVerilog.

COMENTARIOS ADICIONALES/ADDITIONAL COMMENTS:

El contrato es vinculado al proyecto PCI2022-135077-2, financiado por MCIN/AEI/10.13039/501100011033 y por la Unión Europea “NextGenerationEU”/PRTR»